Project-Team:CAIRN

Inria | Raweb 2014 | Presentation of the Project-Team CAIRN | CAIRN Web Site


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Section: Dissemination

Teaching - Supervision - Juries

Teaching

O. Berder: introduction to signal processing, 38h, Enssat (L3)
O. Berder: microprocessors and digital systems, 30h, Enssat (L3)
O. Berder: wireless communications, 23h, Enssat (M2)
O. Berder: ad hoc networks, 58h, Enssat (M1-M2)
O. Berder: signal processing, 12h, IUT Lannion (L2)
E. Casseau: signal processing, 16h, Enssat (L3)
E. Casseau: low power design, 6h, Enssat (M1)
E. Casseau: real time design methodology, 24h, Enssat (M1)
E. Casseau: computer architecture, 36h, Enssat (M1)
E. Casseau: system on chip and verification, 10h, Master by Research (SISEA) and Enssat (M2)
E. Casseau: high level synthesis, 12h, Master by Research (SISEA) and Enssat (M2)
S. Derrien: component and system synthesis, 20h, Master by Research (MRI ISTIC) (M2)
S. Derrien: computer architecture, 12h, ENS Cachan (L3)
S. Derrien: computer architecture, 24h, ISTIC (L3)
S. Derrien: introduction to operating systems, 8h, ISTIC (M1)
S. Derrien: embedded architectures, 48h, ISTIC (M1)
S. Derrien: high-level synthesis, 6h, ISTIC (M1)
S. Derrien: software engineering project, 40h, ISTIC (M1)
F. Charot: processor architecture, 25h University of Science and Technology of Hanoi (M1)
A. Courtay: processor architecture, 24h, Enssat (L3)
A. Courtay: digital electronics, 32h, Enssat (L3)
A. Courtay: digital system design, 12h, Enssat (L3)
A. Courtay: digital electronics communication interfaces, 68h, Enssat (M1)
A. Courtay: processor architecture, 25h, USTH (M1)
D. Chillet: embedded processor architecture, 20h, Enssat (M1)
D. Chillet: VHDL, 10h, Enssat (M1)
D. Chillet: multimedia processor architectures, 24h, Enssat (M2)
D. Chillet: advanced processor architectures, 24h, Master by Research (SISEA) and Enssat (M2)
D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne and University of Occidental Brittany (UBO) (M2)
M. Gautier: electronics, 42h, IUT Lannion (L1)
M. Gautier: telecommunications, 114h, IUT Lannion (L1)
M. Gautier: digital communications, 28h, IUT Lannion (L2)
C. Killian: digital electronics, 37h, IUT Lannion (L1)
C. Killian: signal processing, 36h, IUT Lannion (L2)
C. Killian: automated measurements, 40h, IUT Lannion (L2)
C. Killian: measurement chain, 20h, IUT Lannion (L2)
C. Killian: embedded systems programming, 12h, IUT Lannion (L2)
A. Kritikakou: computer architecture, 50h, ISTIC, Univ. Rennes 1 (L3)
A. Kritikakou: operating systems, 24h, ISTIC, Univ. Rennes 1 (L3)
R. Rocher: electricity, 16h, IUT Lannion (L1)
R. Rocher: electronics, 44h, IUT Lannion (L1)
R. Rocher: telecommunications, 82h, IUT Lannion (L1)
R. Rocher: signal processing, 12h, IUT Lannion (L2)
R. Rocher: digital communications, 48h, IUT Lannion (L2)
P. Scalart: non-linear optimisation, 18h, Master by Research (SISEA) and Enssat (M2)
P. Scalart: parametric modelisation, optimal and adaptive filters, 24h, Master by Research (SISEA) and Enssat (M2)
P. Scalart: source coding, 14h, Master by Research (SISEA) and Enssat (M2)
P. Scalart: cellular networks, 24h, Enssat (M2)
P. Scalart: digital communication systems, 32h, Enssat (M1)
P. Scalart: random signals and systems, 12h, Enssat (M1)
O. Sentieys: digital signal processing, 40h, Enssat (M1)
O. Sentieys: VLSI integrated circuit design, 40h, Enssat (M1)
A. Tisserand: multiprocessor architectures and programming, 20h, Enssat and Master by Research (SISEA) (M2)
A. Tisserand: hardware computer arithmetic operators, 6h, Master by Research (SISEA) (M2)
B. Vrigneau: electronics, 36h, IUT Lannion (L1)
B. Vrigneau: telecommunications, 128h, IUT Lannion (L1)
B. Vrigneau: digital communications, 28h, IUT Lannion (L1)
C. Wolinski: computer architectures, 92h, Esir (L3)
C. Wolinski: design of embedded systems, 48h, Esir (M1)
C. Wolinski: signal, image, architecture, 26h, Esir (M1)
C. Wolinski: programmable architectures, 10h, Esir (M1)
C. Wolinski: component and system synthesis, 10h, Master by Research (MRI ISTIC) (M2)

Teaching Responsibilities

C. Wolinski is the Director of Esir .

P. Quinton is the director of Ecole Normale Supérieure de Rennes.

D. Chillet is the Director of Academic Studies of Enssat .

P. Scalart is the Head of the Electronics Engineering department of Enssat .

S. Derrien is the responsible of the first year of the Master of Computer Science at ISTIC since Sep. 2012.

O. Sentieys is responsible of the ”Embedded Systems” branch of the SISEA Master by Research.

D. Chillet is the responsible of the ICT Master of University of Science and Technology of Hanoi and also co-responsible of the "Embedded Systems" speciality of this master.

Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion.

ISTIC is the Electrical Engineering and Computer Science Department of the University of Rennes 1.

Esir stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

D. Chillet is member of the French National University Council since 2009 in signal processing and electronics (Conseil National des Universités en 61e section).

D. Chillet is member of the Permanent Committee of the French National University Council since November 2011 in signal processing and electronics (Commission Permanente du Conseil National des Universités en 61e section).

A. Tisserand is member of the French National University Council since 2011 in computer science (Conseil National des Universités en 27e section).

Supervision

PhD: Ganda-Stéphane Ouedraogo, Automatic Synthesis of Hardware Accelerator from High-Level Specifications in Flexible Radios, Univ. Rennes 1, Dec. 2014, M. Gautier, O. Sentieys
PhD: Aymen Chakhari, Analytical Accuracy Evaluation in Fixed-Point Digital Communication Systems, Oct. 2014, R. Rocher, P. Scalart.
PhD: Amine Didioui, Energy-Aware Transceiver for Energy Harvesting Wireless Sensor Networks, Oct. 2014, O. Sentieys, C. Bernier.
PhD: Matthieu Texier, Dynamic Parallelism Management in Multi-Core Architectures for Mobile Systems, Dec. 2014, O. Sentieys, C. Bernier.
PhD: Trong-Nhan Le, Global Power Management System for Self-Powered Autonomous Wireless Sensor Nodes, Jul. 2014, O. Sentieys, O. Berder.
PhD: Karim Bigou, RNS Hardware Units for ECC, Nov. 2014, A. Tisserand.
PhD: Pramod P. Udupa, Low Complexity, Parallel Algorithms and Scalable Architectures for Real Time Coherent Optical OFDM Systems, Jun. 2014, O. Sentieys.
PhD in progress: Faycal Ait Aoudia, Power Manager Design and Implementation for Wake-Up Radio WSN Nodes, Oct. 2014, O. Berder, M. Gautier.
PhD in progress: Benjamin Barrois, Approximate Computing: a New Paradigm for Energy-Efficient Computing Architectures, Oct. 2014, O. Sentieys.
PhD in progress: Florent Berthier, Study and Design of an Ultra Low Power Asynchronous Core for Sensor Networks, Oct. 2013, O. Sentieys, P. Vivet, E. Beigne.
PhD in progress: Franck Bucheron, Secure Virtualization for Embedded Systems, Oct. 2011, A. Tisserand.
PhD in progress: Gaël Deest, Computing with Errors: Error-Tolerant Machine Code Generation for Unreliable Embedded Hardware, Oct. 2013, S. Derrien, O. Sentieys.
PhD in progress: Ali Hassan El-Moussawi, Performance/Accuracy Trade-Off in Automatic Parallelization for Embedded Many-Core Platforms, Nov. 2012, S. Derrien.
PhD in progress: Gabriel Gallin, Hardware Arithmetic Units and Crypto-Processor for Hyperelliptic Curves Cryptography, Oct. 2014, A. Tisserand, N. Veyrat-Charvillon.
PhD in progress: Christophe Huriaux, Embedded reconfigurable hardware accelerators with efficient dynamic reconfiguration management, Oct. 2012, O. Sentieys, A. Courtay.
PhD in progress: Quang-Hai Khuat, Real-Time Spatio-Temporal Task Scheduling on 3D Architectures, Oct. 2011, D. Chillet.
PhD in progress: Xuan Chien Le, Indirect Monitoring in Self-Powered Wireless Sensor Networks for Smart Grid and Building Automation, Oct. 2013, O. Sentieys, B. Vrigneau.
PhD in progress: Jiating, Luo, Communication protocol exploration in the context of 3D integration of multiprocessors interconnected by Optical Network-on-Chip with energy constraints, Nov. 2014, D. Chillet, C. Killian, S. Le-Beux.
PhD in progress: Jérémie Métairie, Reconfigurable Arithmetic Units for Secure Cryptoprocessors, Oct. 2012, A. Tisserand, E. Casseau.
PhD in progress: Huu-Van-Long Nguyen, Design and error analysis of robust arithmetic operators for unreliable technologies , Oct. 2014, E. Casseau, A. Tisserand.
PhD in progress: Van-Thiep Nguyen, Energy-efficient MAC protocols for cooperative strategies in Wireless Sensor Networks, Oct. 2013, O. Berder, M. Gautier.
PhD in progress: Viet-Hoa Nguyen, Energy-efficient cooperative techniques for Wireless Body Area Sensor Networks, Nov. 2012, O. Berder, jointly with C. Langlais from Telecom Bretagne.
PhD in progress: Van Dung Pham, Design space exploration in the context of 3D integration of multiprocessors interconnected by Optical Network-on-Chip, Dec 2014, O. Sentieys, D. Chillet, C. Killian, S. Le-Beux.
PhD in progress: Rengarajan Ragavan, Ultra-Low Power Reconfigurable Architectures for Computing and Control in Wireless Sensor Networks, Oct. 2013, O. Sentieys, C. Killian.
PhD in progress: Baptiste Roux, Architectural Exploration of a Low-Power Flexible Radio Embedded on Drones, Oct. 2014, O. Sentieys, M. Gautier.
PhD in progress: Mai-Thanh Tran, Hardware Synthesis of Flexible and Reconfigurable Radio from High-Level Language Dedicated to Physical Layer of Wireless Systems, Oct. 2013, E. Casseau, M. Gautier.
PhD in progress: Zhongwei Zheng, Short-range geolocation algorithms based on distributed multi-sensor processing, Nov. 2012, P. Scalart, jointly with C. Roland from Lab-STICC.

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